The present invention relates to computer graphics systems, and in particular to a method and system for increasing graphics rendering speed and efficiency by offloading rendering operations from a host processor onto a register-based graphics subsystem which can perform graphics rendering on demand with only nominal host processor operations being required.
Generally, computer graphic images are produced by transferring pixel definitions (intensity and color), stored in a memory location known as a frame buffer, to a display screen. Presently, most display systems are raster-based, which means that a value stored in the frame buffer determines the intensity and color of an electron beam at a given pixel, as the beam scans the phosphor-coated inner surface of a display screen at a suitable frequency.
The process of transforming a set of image definitions in program code into a set of pixel values which can be physically displayed on a CRT, and subsequently scanning the pixel values onto a CRT, is often referred to as xe2x80x9crenderingxe2x80x9d. In rendering, a processor must take specifications of graphical primitives, which are the basic building blocks for more complex images, from within an application program and convert them into pixel definitions.
Application programs requiring graphics operations to be performed typically call basic rendering functions for rendering primitives, such as lines, circles and polygons. These basic rendering functions are written in low-level code and reside in a graphics library. A set of basic rendering functions is known as an Application Programmer""s Interface (API), and allows programmers to write graphics applications in a high-level language such as C or Fortran in terms of these basic functions, without the need for writing low-level code. Some standardized and commercially-available API""s include OpenGL, PHIGS (Programmers Hierarchical Graphics Standard), and GKS (Graphical Kernel System).
In order for an image to be rendered, the high-level API specifications within an application program must be interpreted and reduced to hardware-level code. Then, this hardware-level code must be executed to perform the actual physical I/O operations required to fill or modify a frame buffer.
Even with simple images, these tasks can consume significant portions of processor time and system memory. However, graphics applications are becoming increasingly more sophisticated, requiring complex, realistic images to be rendered in color, with lighting, shadow and the like. If certain images are required to be generated repetitively, for example, in the case of a video game, the high demands on processor time and system memory can slow image rendering and frustrate users.
Thus, an approach to rendering is called for that can offload repetitive tasks from a host processor, freeing it to perform other necessary tasks. Specifically, host processor cycles and memory would be conserved, and rendering speed increased, if the host processor operations required to generate hardware-executable instructions from high-level API specifications in a graphics application program could be performed just once for an image required to be rendered repetitively, and the hardware-executable instructions could subsequently be executed on demand to render the image. Such an approach is not known to exist in the prior art.
In the aforesaid related application Ser. No. 09/283,386, assigned to International Business Machines Corporation, having a common inventorship), which is herein incorporated by reference, there is disclosed a method and system for capturing in a memory as an executable program, the hardware instructions to graphics hardware generated by the basic rendering functions called by a graphics application program. Once the hardware instructions are captured, they can be executed on a graphics subsystem to render an image upon demand with only nominal host processor operations being required.
Host processor cycles would further be conserved if hardware interrupt servicing related to graphics operations normally performed by a host processor could be offloaded to a graphics subsystem in a programmable way, i.e., by specifying within a graphics application program, particular hardware interrupt handling routines to be performed by a graphics subsystem rather than the host processor. The method and system according to the related application described above enables such an approach to hardware interrupt handling in graphics operations, which is not known to exist in the prior art.
The present invention provides a method and system for offloading rendering tasks from a host processor to a graphics subsystem which can perform the rendering tasks on demand. A memory is provided which contains captured I/O hardware programs generated by high-level specifications of graphics operations in a computer program. The captured programs are generated and stored in the memory according to the method and system disclosed in the related application described above.
There is further provided a graphics processor which fetches instructions in the captured program and issues them to a graphics accelerator, which executes the intructions to perform graphics operations. The graphics accelerator includes status registers containing status information relating to the graphics operations performed by the accelerator.
A captured program may include instructions for causing the graphics processor to monitor the status information in a status register, and delay issuing instructions in the captured program to the accelerator until specified status information is present in the status register.
The ability to cause the captured programs to execute responsively to the status information allows a programmer to link graphics operations to specific hardware events represented by the status information. Thus, a programmer can code a graphics application to execute graphics operations without initiating host processor hardware interrupt handling routines, by monitoring the status indicator in the graphics accelerator and issuing hardware I/O instructions in the captured programs based on the status information in the indicator. Host processor cycles and memory are thereby conserved, and the efficiency of graphics operations is increased.